MCB11C14【PDF 10/49 页】BOARD EVAL FOR NXP LPC11C14

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NXP Semiconductors

LPC11C12/C14

4 GB

LPC11C12/C14

0xFFFF FFFF

AHB peripherals

0x5020 0000

127- 4 reserved

reserved

0x5004 0000

3

GPIO PIO3

0x5003 0000

AHB peripherals

0x5020 0000

0x5000 0000

2

1

GPIO PIO2

GPIO PIO1

0x5002 0000

0x5001 0000

reserved

0

GPIO PIO0

APB peripherals

0x5000 0000

0x4008 0000

23 - 31 reserved

0x4005 C000

0x4008 0000

22

SPI1

0x4005 8000

1 GB

APB peripherals

0x4000 0000

20

reserved

C_CAN

0x4005 4000

0x4005 0000

reserved

0x4004 C000

reserved

18

17

16

system control

IOCONFIG

SPI0

0x4004 8000

0x4004 4000

0x4004 0000

0.5 GB

reserved

0x2000 0000

0x1FFF 4000

15

14

flash controller

PMU

10 - 13 reserved

0x4003 C000

0x4003 8000

0x4002 8000

16 kB boot ROM

reserved

8 kB SRAM

reserved

0x1FFF 0000

0x1000 2000

0x1000 0000

9

8

7

6

5

4

3

2

1

0

reserved

reserved

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WDT

I 2 C-bus

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

0 GB

32 kB on-chip flash (LPC11C14)

16 kB on-chip flash (LPC11C12)

0x0000 8000

0x0000 4000

0x0000 0000

+ 512 byte

active interrupt vectors

0x0000 0200

0x0000 0000

002aaf268

Fig 3.

LPC11C12/C14 memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

? Controls system exceptions and peripheral interrupts.

? In the LPC11C12/C14, the NVIC supports 32 vectored interrupts including 13 inputs to

the start logic from individual GPIO pins.

LPC11C12_C14_0

Preliminary data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 00.05 — 23 April 2010

? NXP B.V. 2010. All rights reserved.

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